Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration

By K. Bowman, S. Duvall, James D. Meindl. IEEE J. Solid State Circuits, 2002

763 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/37831dcb74a483b06320089602dfcf55513178de

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In Electrical and Electronic Engineering

Citations in the corpus

ASAP7: A 7-nm finFET predictive process design kit (2016, neutral): “Designers will recognize this type of analysis as analogous with critical path timing errors [32].”
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage (2002, background): “In [2] it is shown through statistical simulations that as the number of critical paths per die increases, the within-die delay variation causes the mean frequency to reduce while the variation in critical path delays reduces as well.”
Parameter variations and impact on circuits and microarchitecture (2003, background): “This is consistent with statistical simulation results [1] indicating that”
Physical Unclonable Functions for Device Authentication and Secret Key Generation (2007, background): “It is widely known that significant process variations exist in IC fabrication making each IC unique [3, 4, 10].”
Aegis: A Single-Chip Secure Processor (2007, methodology): “25um technology to be about 3 percent [13].”
VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects (2008, methodology): “This work was supported in part by the National Science Foundation under Grants EIA0072102, EIA-0103610, CHE-0121357, and CCR-0325603, in part by the Defense Advanced Research Projects Agency under Grant NBCH30390004, in part by the DOE under Grant B347886, and in part by gifts from IBM and Intel.”
A 300 nW, 15 ppm/$^{\circ}$C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs (2009, background): “, within-die (WID) (intra-die) variation and die-to-die (D2D) (inter-die) variation [19]–[21].”
Process Variation Tolerant 3T1D-Based Cache Architectures (2007, background): “These assumptions are comparable to the data forecast in [4, 5].”