A Compact Rijndael Hardware Architecture with S-Box Optimization

By Akashi Satoh, Sumio Morioka, Kohji Takano, S. Munetoh. International Conference on the Theory and Application of Cryptology and Information Security, 2001

771 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Computer Networks and Communications, Computer Vision and Pattern Recognition

View Paper: https://www.semanticscholar.org/paper/32b1760aa9da27cfa3b77dac08ff6bba7fb96c7d

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Citations in the corpus

High-speed VLSI architectures for the AES algorithm (2004, methodology): “For example, the composite ﬁeld of can be built iteratively from using the following irreducible polynomials [7]: (7) where and .”
An Optimized S-Box Circuit Architecture for Low Power AES Design (2002, methodology): “Itoh and Tsujii [14] 4.11 1,540 3,490 PPRM (1-stage) 1.32 2,242 408 Twisted-BDD [17] 0.66 1,977 334 BDD 0.96 857 332 Table look-up 0.91 1,706 206 Composite Field [ 10 ] 3.01 305 166 SOP (1-stage) 0.97 1,142 138 Proposed method (3-stage PPRM) 1.86 701 51 An Optimized S-Box Circuit Architecture for Lo”
A Side-Channel Analysis Resistant Description of the AES S-Box (2005, methodology): “In [12], other field polynomials have been chosen that lead to a less efficient finite field arithmetic.”
New Lightweight DES Variants (2007, methodology): “If we compare a standard, one-round implementation3 of AES and DES, the latter consumes about 6% (!) of the logic resources of AES, while having a shorter critical path [VHVM88],[ ASM01 ].”
Fault Based Cryptanalysis of the Advanced Encryption Standard (AES) (2003, methodology): “This means in particular, that such AES hardware modules really compute the AES operations ByteSub, MixColumn and of course xtime, instead of using large ROM based lookup tables to compute the corresponding transformations, cf. [ SMTM ,Wo,WOL].”
Very Compact FPGA Implementation of the AES Algorithm (2003, methodology): “[23] proposed an implementation based on the following idea:”
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core (2006, methodology): “A number of iterative AES ASIC designs with varying data path widths are reported in [14].”
Midori: A Block Cipher for Low Energy (2015, background): “The past few years have seen several low-power/area architectures for AES being reported in literature [28,31,18].”
Side-Channel Leakage of Masked CMOS Gates (2005, methodology): “However, for implementations of operations like the AES S-Box, nonlinear operations are crucial (see [18] and [25]).”
$\textnormal{\textsc{TWINE}}$ : A Lightweight Block Cipher for Multiple Platforms (2012, methodology): “While AES has been widely deployed and we can see constant efforts for smallfootprint AES, such as [13, 30, 39], AES is often inappropriate for such small devices due to their size/power/memory constraints.”