Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
By Panu Hämäläinen, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen. Euromicro Symposium on Digital Systems Design, 2006
298 citations recorded by the source corpus.
Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition, Signal Processing
View Paper: https://www.semanticscholar.org/paper/80651e9335454185f2c07de38e81eee2bbbe6bde
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In Artificial Intelligence
- Axel York Poschmann
- Christof Paar
- Kyoji Shibutani
- Toru Akishita
- Harunaga Hiwatari
- Takanori Isobe
- San Ling
- Zheng Gong
In Computer Vision and Pattern Recognition
- Axel York Poschmann
- San Ling
- Zheng Gong
- Svetla Nikova
- Amir Moradi
- Huaxiong Wang
- Yee Wei Law
- Christof Paar
In Signal Processing
Citations in the corpus
- Pushing the Limits: A Very Compact and a Threshold Implementation of AES (2011, methodology): “Low-power low-area implementations of the AES have been reported in [15] requiring 3100 GE and 160 clock cycles and in [13] requiring 3400 GE and 1032 clock cycles.”
- Piccolo: An Ultra-Lightweight Blockcipher (2011, methodology): “Our serialized implementation is based on 4-bit shift registers in the similar way as [18].”
- KATAN and KTANTAN - A Family of Small and Efficient Hardware-Oriented Block Ciphers (2009, unknown): “35 μm AES-128 [10] 128 128 3100 5.”
- KLEIN: A New Family of Lightweight Block Ciphers (2010, background): “[24] (with 3100 GE) and Feldhofer et al.”