An Optimized S-Box Circuit Architecture for Low Power AES Design

By Sumio Morioka, Akashi Satoh. Workshop on Cryptographic Hardware and Embedded Systems, 2002

306 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/f69a2b7c49d58b8d4b9da269f939f2486eca61a1

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Artificial Intelligence

1. David Canright
2. Kris Gaj
3. Tymur A. Korkishko
4. Pawel Chodowiec
5. Chae Hoon Lim
6. Svetla Nikova
7. Timo D. Hämäläinen
8. Marko Hännikäinen

In Electrical and Electronic Engineering

1. Kris Gaj
2. David Canright
3. Tymur A. Korkishko
4. Pawel Chodowiec
5. Chae Hoon Lim

In Hardware and Architecture

1. Kris Gaj
2. David Canright
3. Tymur A. Korkishko
4. Pawel Chodowiec
5. Chae Hoon Lim

Citations in the corpus

• Very Compact FPGA Implementation of the AES Algorithm (2003, methodology): “[10] went even farther and proposed a low-power compact S-box design suited for ASIC designs.”
• A Very Compact S-Box for AES (2005, background): “Some approaches seek to maximize throughput, e.g., [7], [16] and [3]; others minimize power consumption, e.g., [ 8 ]; and yet others minimize circuitry, e.g., [13], [14], [17], and [2].”
• mCrypton - A Lightweight Block Cipher for Security of Low-Cost RFID Tags and Sensors (2005, methodology): “Clearly we would have to sacrifice the circuit size more or less to apply power consumption minimization strategies (e.g., see [ 8 ]).”