Transactional memory coherence and consistency

By Lance Hammond, Vicky Wong, Michael K. Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, Kunle Olukotun. Proceedings. 31st Annual International Symposium on Computer Architecture, 2004., 2004

771 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/2c1ea92d6a4237ede5ea112f1880710b25bec8b3

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Citations in the corpus

Unbounded transactional memory (2005, background): “Moreover, it confirms other researchers’ findings [10, 31, 32] that transactions can execute with lower overhead than locks.”
Transactional Memory, 2nd edition (2010, methodology): “We look, in particular, at systems such as LogTM that use software-managed logs to hold updates [227], systems such as Bulk that use Bloom-filter signatures for conflict detection [53], systems such as TCC that decouple conflict checks from cache coherence protocols [132], and systems such as FlexTM”
Alpaca: intermittent execution without checkpoints (2017, background): “Transactions [Gray and Reuter 1992] and, in particular, transactional memory [Hammond et al. 2004; Harris et al. 2005; Herlihy and Moss 1993; Shavit and Touitou 1995] (TM) systems are also related to Alpaca.”
Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation (2011, background): “Many research studies assume a one-IPC model when studying for example memory hierarchy optimizations, the interconnection network and cache coherency protocols in large-scale multiprocessor and multi-core systems [15, 23, 17].”
Hybrid transactional memory (2006, background): “Based on studies in the literature [3, 7, 23], we expect that in many cases almost all transactions will not overflow on-chip resources, and thus neutered performance will closely track unneutered performance, even for more realistic codes.”
AVIO: detecting atomicity violations via access interleaving invariants (2006, positive): “Recently there is an emerging trend toward transactional memory programming model via hardware or software support [1, 13, 16, 18].”
A simpler, safer programming and execution model for intermittent systems (2015, background): “DINO’s tasks are akin to transaction regions in TCC [15], which require only that programmers insert transaction boundaries into their code and provides transactional semantics via hardware enhancements, or bulk-sequential chunks as in BulkSC [7].”
Learning from mistakes: a comprehensive study on real world concurrency bug characteristics (2008, neutral): “Along this direction, transactional memory (TM) [1,2,15,16,25,26,27,36] is one of the popular trends.”
Bulk Disambiguation of Speculative Threads in Multiprocessors (2006, methodology): “, [2, 12, 13, 18, 20]), threads are typically obtained from a parallel program, and become speculative when they enter a transaction.”
Transactional Locking II (2006, background): “Providing large scale transactions in hardware tends to introduce large degrees of complexity into the design [1–4].”
LogTM: log-based transactional memory (2006, methodology): “’s Transactional Memory Coherence and Consistency (TCC) [11] uses both lazy version management and lazy conflict detection, similar to the few database management systems (DBMSs) that use optimistic concurrency control (OCC) [16].”
STAMP: Stanford Transactional Applications for Multi-Processing (2008, methodology): “• Lazy HTM: This is an HTM system that follows the TCC architecture [16], except that transactions are only executed for code sections demarcated by transaction boundary markers instead of all code sections.”
Transactional boosting: a methodology for highly-concurrent transactional objects (2008, methodology): “This approach has been investigated in hardware [1, 8, 14, 24, 23], in software [9, 10, 13, 21, 31], and in schemes that mix hardware and software [6, 28].”
LogTM-SE: Decoupling Hardware Transactional Memory from Caches (2007, background): “These demands include read/write (R/W) bits for read- and write-set tracking [3, 11, 19, 25], flash clear operations at commits/aborts [3, 11, 19, 25], and write buffers for speculative data [7, 11].”
Optimistic parallelism requires abstractions (2007, background): “Most of this work is concerned with optimistic synchronization and not optimistic parallelization; that is, their starting point is a program that has already been parallelized (for example, the SPLASH benchmarks [12] or the Linux kernel [28]), and the goal is find an efficient way to synchronize pa”