LogTM: log-based transactional memory

By Kevin E. Moore, Jayaram Bobba, M. Moravan, Mark D. Hill, David A. Wood. The Twelfth International Symposium on High-Performance Computer Architecture, 2006., 2006

730 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/90665e68bcd06c218932ba461ccc9467f0bc1f39

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Citations in the corpus

Transactional memory (2010, methodology): “The transactional memory state can Table 1: A classiﬁcation of hardware transactional memory proposals, structured the same way as in [10].”
Mnemosyne: lightweight persistent memory (2011, methodology): “The Mnemosyne transaction system implements lazy version management [46] with write-ahead redo logging, and eager conflict detection [46] with encounter-time locking.”
Hybrid transactional memory (2006, methodology): “[22] have proposed LogTM, which stores tentative new values “in place”, while maintaining logs to facilitate undoing changes made by a transaction in case it aborts.”
Optimistic parallelism requires abstractions (2007, background): “There is growing interest in supporting transactions efficiently with software and hardware implementations of transactional memory [1, 12, 13, 21, 34].”
STAMP: Stanford Transactional Applications for Multi-Processing (2008, background): “• Eager HTM: An HTM system similar to LogTM [29].”
An effective hybrid transactional memory system with strong isolation guarantees (2007, methodology): “To implement SigTM correctly in such systems, we can use the LogTM sticky directory states [20].”
Transactional Memory, 2nd edition (2010, methodology): “[227] introduced the use of software-resident logs for version management in an HTM.”
LogTM-SE: Decoupling Hardware Transactional Memory from Caches (2007, methodology): “If an L1 cache replaces transactional data, the L2 cache does not update the exclusive pointer or sharer’s list (like the sticky-S and sticky-M states in LogTM [19]).”
Bulk Disambiguation of Speculative Threads in Multiprocessors (2006, methodology): “, [2, 12, 13, 18, 20]), threads are typically obtained from a parallel program, and become speculative when they enter a transaction.”
Learning from mistakes: a comprehensive study on real world concurrency bug characteristics (2008, neutral): “Along this direction, transactional memory (TM) [1,2,15,16,25,26,27,36] is one of the popular trends.”
Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation (2011, background): “Many research studies assume a one-IPC model when studying for example memory hierarchy optimizations, the interconnection network and cache coherency protocols in large-scale multiprocessor and multi-core systems [15, 23, 17].”