Use of negative capacitance to provide voltage amplification for low power nanoscale devices.

By Sayeef Salahuddin, Supriyo Datta. Nano letters (Print), 2008

1,885 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/216e8f12492bd11ad7047de6080d6bcd6d195aa0

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Uwe Schroeder
2. Thomas Mikolajick
3. Stefan Slesazeck
4. Changhwan Shin
5. Jaesung Jo
6. Asif Islam Khan
7. Chenming Calvin Hu
8. Heike E. Riel

Citations in the corpus

• Low-Voltage Tunnel Transistors for Beyond CMOS Logic (2010, neutral): “Switching mechanisms that can achieve less than 60 mV/decade in a FET structure include tunneling [4]–[6], impact ionization [7]–[10], ferroelectric dielectrics [11], or mechanical gates [12]–[14].”
• Sub-60mV-swing negative-capacitance FinFET without hysteresis (2015, background): “Planar NCFET with 60 mV/decade subthreshold swing (SS) has been reported using an organic ferroelectric material [3].”
• Physics-Based Circuit-Compatible SPICE Model for Ferroelectric Transistors (2016, neutral): “1) [1].”
• Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics (2016, background): “If |CFE| becomes smaller than CMOS, hysteresis is expected [1], [2].”