NeuFlow: Dataflow vision processing system-on-a-chip

By Phi-Hung Pham, D. Jelača, Clément Farabet, Berin Martini, Yann LeCun, Eugenio Culurciello. 2012

94 citations recorded by the source corpus.

Subfields: Cellular and Molecular Neuroscience, Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, ML Systems & Hardware

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Cellular and Molecular Neuroscience

In Computer Vision and Pattern Recognition

In Electrical and Electronic Engineering

In ML Systems & Hardware

Citations in the corpus

Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activations (2016, background): “…research efforts are invested in speeding up DNNs at run-time on both generalpurpose (Vanhoucke et al., 2011; Gong et al., 2014; Romero et al., 2014; Han et al., 2015b) and specialized computer hardware (Farabet et al., 2011a,b; Pham et al., 2012; Chen et al., 2014a,b; Esser et al., 2015).”
Binarized Neural Networks (2016, background): “, 2015) and specialized computer hardware (Farabet et al., 2011a;b; Pham et al., 2012; Chen et al., 2014a;b; Esser et al., 2015).”
DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients (2016, background): “…light of this, substantial research efforts are invested in speeding up DCNNs at both run-time and training-time, on both general-purpose (Vanhoucke et al., 2011; Gong et al., 2014; Han et al., 2015b) and specialized computer hardware (Farabet et al., 2011; Pham et al., 2012; Chen et al., 2014a;b).”
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars (2016, background): “A number of works have designed hardware neural networks and neuromorphic circuits using analog computation [5], [29], [52], [60], [61], [72] to take advantage of faster vector-matrix multiplication [18], [56].”
Training deep neural networks with low precision multiplications (2014, background): “FPGA and ASIC implementations claim a better power efficiency than general-purpose hardware (Kim et al., 2009; Farabet et al., 2011; Pham et al., 2012; Chen et al., 2014a;b).”
Origami: A Convolutional Network Accelerator (2015, methodology): “The ASIC implementation of neuFlow comes with 299 I/O pins to achieve 300 GOp/s. Applying the aforementioned scene labeling ConvNet to larger images such as full-HD frames requires 5190 GOp/s to get 20 frame/s and there is also a trend towards even more complex ConvNets.”
YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights (2016, methodology): “For computational complexity the total number of multiplications and additions have been used in other publications like in [36], [11], [33], [8].”
YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration (2016, methodology): “Even though most approaches work with ﬁxed-point operations, the number of quantization bits is still kept at 24-bit [28], [40] or 16-bit [17], [18], [27], [42], [45].”
BinaryNet: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1 (2016, background): “…devices, and much research work is done to speed-up DNNs at run-time on both general-purpose (Vanhoucke et al., 2011; Gong et al., 2014; Romero et al., 2014; Han et al., 2015) and specialized computer hardware (Farabet et al., 2011a;b; Pham et al., 2012; Chen et al., 2014a;b; Esser et al., 2015).”
Effective Quantization Methods for Recurrent Neural Networks (2016, methodology): “To alleviate these requirements, many methods have been proposed, from both hardware and software perspective (Farabet et al., 2011; Pham et al., 2012; Chen et al., 2014a;b).”
Memory and Information Processing in Neuromorphic Systems (2015, methodology): “Such networks have also been linked to the Dynamic Neural Fields (DNFs) typically used to model behavior and cognition in autonomous agents [107], [108].”
RedEye: Analog ConvNet Image Sensor Architecture for Continuous Mobile Vision (2016, background): “Hardware ConvNet acceleration: Many convolutional architectures are focused on reconfigurable flexibility [30]– [32].”