Stable SRAM cell design for the 32 nm node and beyond
By L. Chang, D. Fried, J. Hergenrother, J. Sleight, R. Dennard, R. Montoye, L. Sekaric, S. Mcnab, Anna W. Topol, C. Adams and 2 more. Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 2005
618 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/10b3a5ed39d3a164374c4bbbe70385bd0b211d9f
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In Electrical and Electronic Engineering
- Anantha P. Chandrakasan
- Naveen Verma
- Wilfried E. Haensch
- Wim Dehaene
- Massimo Alioto
- Mohamed F. Younis
- Xuxun Liu
- Deborah Estrin
Citations in the corpus
- Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies (2006, background): “Digital Object Identifier 10.1109/JSSC.2006.883344 the cell stability for future technology nodes [4].”
- Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia (2008, background): “, 8-Transistor [16]) may replace the traditional 6T scheme, with all the consequences to integration density.”
- An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches (2008, background): “Even if the cell ratio for a 6T cell is increased [5] (thus trading off cell area to match that of the 8T), the 8T still provides a considerably improved static noise margin (Fig.”
- A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications (2006, methodology): “To avoid this limitation, the use of a dual-port SRAM cell as a single-port SRAM has been proposed [6].”
- A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy (2008, background): “Consequently, the read SNM limitation from Section II-A is eliminated [10].”