A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications

By K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, Toshio Ishii, H. Kobatake. IEEE Journal of Solid-State Circuits, 2006

319 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/0e820f7fd2fee926b1e1140ffa58290b87d95514

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Massimo Alioto
2. Wilfried E. Haensch
3. Anantha P. Chandrakasan
4. Benton H. Calhoun
5. Mohamed F. Younis
6. Xuxun Liu
7. Deborah Estrin
8. Ian F. Akyildiz

In Hardware and Architecture

1. Massimo Alioto

Citations in the corpus

• An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches (2008, background): “While other cell options have been proposed in the literature for variability tolerance, they generally carry considerable tradeoffs in floorplanning [7] or cell size”
• A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation (2007, background): “Cell stability during active operation represents a more significant limitation to SRAM operation than during hold.”
• Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial (2012, background): “A 7T cell was proposed in [63] that enables”