A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

By Naveen Verma, Anantha P. Chandrakasan. IEEE Journal of Solid-State Circuits, 2008

477 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/fe588150501276e4e4adaaa4baf1d508e06be622

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In Electrical and Electronic Engineering

1. Massimo Alioto
2. Benton H. Calhoun

Citations in the corpus

• A Batteryless 19 $\mu$W MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications (2013, background): “2) Instruction and Data Memories: Because the chip operates in subthreshold in an N-strong technology, the SRAMs use an 8 T bitcell and the zero leakage read-buffer from [18].”
• Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial (2012, background): “The above discussed read buffer permits to decouple the write and read margins, and the read margin becomes essentially equal to the hold margin [44], [58], [59].”