Memory-centric accelerator design for Convolutional Neural Networks

By Maurice Peemen, Arnaud Arindra Adiyoso Setio, B. Mesman, Henk Corporaal. 2013

315 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, Hardware and Architecture

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Citations in the corpus

A 64-mW DNN-Based Visual Navigation Engine for Autonomous Nano-Drones (2018, background): “However, this effort does not curtail the difficulty of effectively deploying DNNs in memory-scarce platforms, which often requires particular scheduling/tiling [29], [30] and is still widely considered an open problem.”
FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks (2017, background): “In [20], a flexible memory hierarchy is proposed to support different kinds of parallelism and to improve the efficiency of on-chip memory.”
Fused-layer CNN accelerators (2016, methodology): “The computational dominance of the convolutional layers, coupled with the need for larger and deeper networks, has sparked significant interest in the design and optimization of accelerator structures for these layers [19], [10].”
Minimizing Computation in Convolutional Neural Networks (2014, background): “, GPUs and field-programmable gate arrays (FPGAs) [3,5,9].”
Energy-efficient ConvNets through approximate computing (2016, background): “A number of ConvNet hardware optimizations [2] [15], coprocessors [6] and accelerators such as DianNao [1] have been proposed.”
Maximizing CNN accelerator efficiency through resource partitioning (2016, background): “Meanwhile, [18, 19] use FMA units for computation.”
Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs (2017, methodology): “Traditional methods apply loop unrolling on multiple for-loops to enable massive parallelization [6] and perform memory partitioning to feed the multiple data into different DSP blocks [5].”
A high performance FPGA-based accelerator for large-scale convolutional neural networks (2016, background): “Hence, general purpose processors are not so efficient while a number of CNN implementations based on GPU [1], FPGA [7, 8, 9, 10, 11, 12, 13, 14, 15] even ASIC [16, 17, 18, 19] have been proposed.”
TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory (2017, methodology): “There were several recent proposals for CNN accelerators using ASIC or FPGA platforms [33, 34].”
Adaptive Convolutional Neural Network and Its Application in Face Recognition (2015, unknown): “To solve this problem, some studies are on hardware acceleration, which is made to speed up the performance comparison, for instance, GPU-based programming and scalable hardware architecture [5–7].”
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks (2015, background): “Among these approaches, FPGA based accelerators have attracted more and more attention of researchers because they have advantages of good performance, high energy efficiency, fast development round, and capability of reconfiguration [1] [2] [3] [6] [12] [14].”
A survey of FPGA-based accelerators for convolutional neural networks (2018, background): “However, large on-chip memories are not energy efﬁcient [19], and thus, the on-chip memory has limited effectiveness.”