Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks

By Chen Zhang, Peng Li, Guangyu Sun, Yijin Guan, Bingjun Xiao, Jason Cong. 2015

2,074 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Electrical and Electronic Engineering

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Artificial Intelligence

In Electrical and Electronic Engineering

Citations in the corpus

A 64-mW DNN-Based Visual Navigation Engine for Autonomous Nano-Drones (2018, background): “However, this effort does not curtail the difficulty of effectively deploying DNNs in memory-scarce platforms, which often requires particular scheduling/tiling [29], [30] and is still widely considered an open problem.”
EIE: Efficient Inference Engine on Compressed Deep Neural Network (2016, methodology): “…total power to around 10W in 28nm, compared to EIEs power of 0.58W in 45nm. Previous DNN accelerators targeting ASIC and FPGA platforms [10] [41] used mostly CONV layer as benchmarks, but have few dedicated experiments on FC layers, which has signiﬁcant bandwidth bottlenecks, and is widely…”
Pipe-SGD: A Decentralized Pipelined SGD Framework for Distributed Deep Net Training (2018, background): “The fraction of time spent on communication is further increased when applying accelerators [16, 7, 38, 52, 48, 49, 44], as they decrease computation time while leaving communication time untouched.”
A Survey and Evaluation of FPGA High-Level Synthesis Tools (2016, positive): “, medical imaging, convolutional neural networks, and machine learning), with significant benefits in terms of performance and energy consumption [5].”
Deep Learning on FPGAs: Past, Present, and Future (2016, background): “Other strong eﬀorts include the design proposed by Zhang et al., referenced above as the closest competitor achieving a throughput of 46 images/second on a Virtex 7 485T, with an unreported power consumption [36].”
DeepX: A Software Accelerator for Low-Power Deep Learning Inference on Mobile Devices (2016, methodology): “Although, DeepX is not tested on purpose built hardware for deep learning [41], [45], our software approach to accelerating models in general should apply in this case.”
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network (2017, background): “Due to their insatiable demand for compute power, naturally, both the research community [1–28] as well the industry [29–31] have turned to accelerators to accommodate modern DNN computation.”
Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating (2019, methodology): “If the network contains convolutional filters of different sizes, techniques similar to [15] can be used to choose an optimal value of P .”
Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs (2017, methodology): “In this section we brieﬂy review the basic principles and terminology of CNNs, the differences between a CNN and BNN, and the speciﬁc CIFAR-10 BNN model that our accelerator will target.”
Domain-specific Genetic Algorithm for Multi-tenant DNNAccelerator Scheduling (2021, background): “While there has been significant prior work on scheduling a single DNN model efficiently over one (or more distributed) accelerators [65, 95, 100, 102, 115, 122], scheduling multiple models simultaneously is relatively unexplored, and is the focus of this work.”
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference (2016, methodology): “[31] but explore binary weights for fixed sized windows.”
Fathom: reference workloads for modern deep learning methods (2016, neutral): “Category Feature [8] [9] [10] [11] [12] [14] [21] [24] [26] [35] [38] [39] [40] [44] [47] [49] Fathom”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, neutral): “…[24–27], Cambricon [28], Cambricon-x [29], TPU [30,31], ScaleDeep [32], Stripes [33], Neural Cache [123,124], Diffy [125] FPGA FPGA-DCNN [34], Embedded-FPGA-CNN [35], FPGA-Exploration [36], OpenCL-FPGA-CNN [37] [126], Caffeine [38], DeepBurning [39], FPGA-DPCNN [40], TABLA [41],…”
Recent Advances in Convolutional Neural Network Acceleration (2018, background): “Roofline-model-based accelerator [123] VC707 FPGA 100MHz 61.”
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA (2016, background): “Currently, the most widely used neural models of deep learning are deep neural networks (DNNs) [2] and convolution neural networks (CNNs) [3], which have been proved to have excellent capability in solving picture recognition, voice recognition, and other complex machine learning tasks.”
Hardware/Software Co-Exploration of Neural Architectures (2019, neutral): “Finally, for both data and weights, we apply the commonly used 16-bit fixed-point data, as that in [21], [29], [30], and [39].”
FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks (2017, background): “Styles Architectures SFSNMS DC-CNN [1], CNP [8], Neuflow [7] SFMNSS Diannao [2], DaDiannao [3], FPGA15 [29] MFSNSS ShiDiannao [6]”