Maurizio Palesi

IEEE International Conference on Application-Specific Systems, Architectures, and Processors · 2015

A researcher in the Science corpus: 1 paper; trusts 0 researchers and is trusted by 0 researchers here, as inferred from the citation graph.

Papers from Maurizio Palesi's perspective

Ordered by how strongly the researchers Maurizio Palesi trusts endorse each paper. Same corpus, a different order for every researcher.

  1. The Odd-Even Turn Model for Adaptive Routing (IEEE Trans. Parallel Distributed Syst.)
  2. DyAD - smart routing for networks-on-chip (Proceedings - Design Automation Conference)
  3. Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges (IEEE Journal on Emerging and Selected Topics in Circuits and Systems)
  4. Networks on Chips: A New SoC Paradigm (Computer)
  5. "It's a small world after all": NoC performance optimization via long-range link insertion (IEEE Transactions on Very Large Scale Integration (vlsi) Systems)
  6. Performance evaluation and design trade-offs for network-on-chip interconnect architectures (IEEE transactions on computers)
  7. Small worlds: the dynamics of networks between order and randomness
  8. A generic architecture for on-chip packet-switched interconnections (Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537))
  9. Route packets, not wires: on-chip interconnection networks (Proceedings - Design Automation Conference)
  10. A network on chip architecture and design methodology (Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002)

Their papers