Transient fault detection via simultaneous multithreading

By Steven K. Reinhardt, Shubhendu S. Mukherjee. Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), 2000

714 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/fe5f9758b6212e649f88e3a7b32973119b9ee4ea

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Citations in the corpus

SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery (2002, background): “Processor faults can be detected with numerous schemes, including parity, redundant ALUs, and redundant threads [35, 37, 42].”
Design for soft error mitigation (2005, methodology): “Multithreading is another software-based transient fault detection and recovery approach [ 24 ], [25] that reduces memory and speed cost by exploiting the capabilities of modern processors to execute multiple threads of computation.”
Techniques to reduce the soft error rate of a high-performance microprocessor (2004, neutral): “, [3], [22], [20], [29], [17], [8], [19], [14]).”
The soft error problem: an architectural perspective (2005, neutral): “In RMT, outputs of selected committed instructions are checked for mismatch at commit point of instructions [ 12 ].”
Transient-fault recovery for chip multiprocessors (2003, methodology): “CRTR uses the previou proposed Load Value Queue [9] to communicate the leadi load values to the trailing thread.”
Transient-fault recovery using simultaneous multithreading (2002, methodology): “SRT formalizes this notion by defining thesphere of replication (SoR) [10], pointing out that (1) all computation and data within this sphere are replicated such that each thread uses its own copy, (2) data entering the SoR is independently read by the two threads usinginput replication, (3) data ex”
SWIFT: software implemented fault tolerance (2005, methodology): “Though no direct comparison is made to multithreaded approaches, it performson par with hardware multithreading-based redundancy techniques [19] without the additional hardware cost.”
Slipstream processors: improving both performance and fault tolerance (2000, background): “DIVA [2] and SRT [22] are two other examples of fault-tolerant architectures designed for commodity high-performance microprocessors.”
Gate sizing to radiation harden combinational logic (2006, background): “More recently, solutions like simultaneous and redundant multithreading (SRT) [30], [36], active-stream/redundant-stream simultaneous multithreading (AR-SMT) [31], and slipstream processors [28] have been proposed to exploit the significant amount of redundancy, repetition , and predictability in ge”
ReStore: symptom based soft error detection in microprocessors (2005, background): “branch predictions) and can provide input replication to ensure correctness during reexecution (e.g. Load Value Queues [ 24 ]).”
Shoestring: probabilistic soft error reliability on the cheap (2010, methodology): “Implicit is the assumption that the sphere of replication (SoR) [ 24 ], or the scope beyond which a technique cannot tolerate faults, is limited to the processing core.”