Transient-fault recovery for chip multiprocessors
By Mohamed A. Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz. 30th Annual International Symposium on Computer Architecture, 2003. Proceedings., 2003
372 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/118c7c25942d75313581de7a034634925a521ef9
How researchers see this paper
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In Computer Networks and Communications
- Joel S. Emer
- Scott A. Mahlke
- Shuguang Feng
- Shantanu Sen Gupta
- Amin Ansari
- Ram Rangan
- George A. Reis
- Neil Vachharajani
In Electrical and Electronic Engineering
- Joel S. Emer
- Scott A. Mahlke
- Shuguang Feng
- Shantanu Sen Gupta
- Amin Ansari
- Ram Rangan
- George A. Reis
- Neil Vachharajani
Citations in the corpus
- Techniques to reduce the soft error rate of a high-performance microprocessor (2004, background): “, [2], [29], [8]) requires duplication of a thread or processor.”
- SWIFT: software implemented fault tolerance (2005, methodology): “[4] expanded that approach with CRTR to enable recovery.”
- A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor (2003, background): “Finally, Gomaa, et al.’s CRTR design [ 10 ] relies on logical masking to avoid fault detection checks on certain logical instructions.”
- Shoestring: probabilistic soft error reliability on the cheap (2010, background): “Other research has focused on providing fault protection using redundant multithreading [8, 17, 24, 27, 30] or hardware checkers like DIVA [6, 39].”