Slipstream processors: improving both performance and fault tolerance

By K. Sundaramoorthy, Zachary Purser, Eric Rotenberg. SIGP, 2000

345 citations recorded by the source corpus.

Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effect. We propose creating a shorter but otherwise equivalent version of the original program by removing ineffectual computation and computation related to highly-predictable control flow. The shortened program is run concurrently with the full program on a chip multiprocessor or simultaneous multithreaded processor, with two key advantages:1) Improved single-program performance. The shorter program speculatively runs ahead of the full program and supplies the full program with control and data flow outcomes. The full program executes efficiently due to the communicated outcomes, at the same time validating the speculative, shorter program. The two programs combined run faster than the original program alone. Detailed simulations of an example implementation show an average improvement of 7% for the SPEC95 integer benchmarks.2) Fault tolerance. The shorter program is a subset of the full program and this partial-redundancy is transparently leveraged for detecting and recovering from transient hardware faults.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/48a68bb6f76435c65c8c23683766aeab67183b1a

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Citations in the corpus

N-Variant Systems: A Secretless Framework for Security through Diversity (2006, background): “Slipstream processors are an interesting variation of this, where two redundant versions of the instruction stream execute, but instructions that are dynamically determined to be likely to be unnecessary are removed from the first stream which executes speculatively [60].”
Detailed design and evaluation of redundant multi-threading alternatives (2002, methodology): “[26] proposed the use of RMT techniques on dualprocessor CMP cores.”
Transient-fault recovery for chip multiprocessors (2003, methodology): “AR-SMT and Slipstream briefly mention recovery using their equivalent of the trailing thread in SMT and CMP, respectively.”
Transient-fault recovery using simultaneous multithreading (2002, methodology): “A later paper applies the concepts from AR-SMT to CMPs [15].”
SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery (2002, background): “For example, redundant processors [4, 26, 27, 45] or redundant threads within a processor [42] can be used to mask processor faults.”
Speculative precomputation: long-range prefetching of delinquent loads (2001, background): “proposed Slipstream Processors [17], in which a non-speculative version of a program runs alongside a shortened, speculative version.”