Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI)

By A. Naeemi, Reza Sarvari, James D. Meindl. IEEE Electron Device Letters, 2005

314 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials, Materials Chemistry

View Paper: https://www.semanticscholar.org/paper/f6628b40658f2994c90b317339f44e513bb384a6

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Citations in the corpus

Design and Performance Modeling for Single-Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems (2007, background): “copper wires was first compared in [14] and [15], where it was demonstrated that SWCN bundles can have adequately large propagation speed and outperform copper wires in terms”
Compact physical models for multiwall carbon-nanotube interconnects (2006, background): “S INGLE- AND MULTIWALL carbon nanotubes (SWCN and MWCN) are being extensively investigated for interconnect applications as they can conduct very large current densities and have electron mean free paths (mfps) in the micrometer range [1]–[3].”
Performance analysis of carbon nanotube interconnects for VLSI applications (2005, background): “However, it can easily be shown that a low voltage bias is always applicable in the domain of VLSI interconnect applications, as has also been argued in [25].”
On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects (2009, result): “compared with Cu has been shown in [39] and [40].”
Electrical and thermal transport in metallic single-wall carbon nanotubes on insulating substrates (2006, background): “Several recent studies have analyzed the promise of metallic SWNTs as circuit elements [6-9].”
A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region (2007, background): “909030 CNT for interconnects [11], [12] in order to evaluate the po-”
Evaluating the impact of resistance in carbon nanotube bundles for VLSI interconnect using diameter-dependent modeling techniques (2006, background): “not considered the distribution of metallic and semiconducting nanotubes within the bundle [5], [14], [15].”