Performance analysis of carbon nanotube interconnects for VLSI applications

By Navin Srivastava, Kaustav Banerjee. ICCAD. IEEE/ACM International Conference on Computer-Aided Design, 2005

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Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects (2008, background): “From the aforementioned discussions and the results from previous SWCNT interconnect modeling works [14]–[17], it can be concluded that both SWCNT and MWCNT interconnects can achieve better performance than Cu wires for long lengths.”
High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design (2009, methodology): “Since the impact of kinetic inductance has raised some concerns in terms of its significance [6], [21], its fraction in the total effective inductance of CNT interconnects for different cross sections has been analyzed at low frequency (where inductance will not change with frequency) using our meth”
Evaluating the impact of resistance in carbon nanotube bundles for VLSI interconnect using diameter-dependent modeling techniques (2006, background): “bundle studies have either not considered or overestimated the resistance resulting from imperfect metal to nanotube contacts [5], [14]–[16].”
Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects (2009, methodology): “45 kΩ for an SWCNT) necessitates the use of a bundle (rope) of CNTs [64], [65], conducting”
On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects (2009, unknown): “The work in [41] Fig.”