A dynamically configurable coprocessor for convolutional neural networks

By Srimat T. Chakradhar, Murugan Sankaradass, Venkata Jakkula, Srihari Cadambi. 2010

387 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, Neurology

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Citations in the corpus

Project Adam: Building an Efficient and Scalable Deep Learning Training System (2014, background): “The vision and computer architecture community has started to explore hardware acceleration for neural network models for vision [3, 4, 10, 16, 22].”
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks (2016, neutral): “Keywords FPGA, OpenCL, Convolutional Neural Networks, Optimization.”
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks (2015, methodology): “Among these approaches, FPGA based accelerators have attracted more and more attention of researchers because they have advantages of good performance, high energy efficiency, fast development round, and capability of reconfiguration [1] [2] [3] [6] [12] [14].”
FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks (2017, background): “Systolic and 2D-Mapping also equip local stores.”
Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer (2017, methodology): “[24]–[28] use various dataflows that are optimized for performing 2D-convolutions.”
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, methodology): “employed to automatically configure both the software and the hardware elements to fully exploit parallelism [100].”
Going Deeper with Embedded FPGA Platform for Convolutional Neural Network (2016, methodology): “To address this problem, many researchers have proposed various CNN acceleration techniques from either computing or memory access aspects [6, 7, 8, 9, 10, 11, 12, 13].”
Memory-centric accelerator design for Convolutional Neural Networks (2013, methodology): “Recently, two design proposals were built around systolic implementations of the 2d convolution operation: NEC labs developed a convolutional coprocessor [10] and an accelerator design is reported in [11].”
Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks (2016, background): “Most prior FPGA acceleration studies on CNN [13, 15–21] mainly focus on the convolution layer in CNN, since it is computation-bound and is the most timing-consuming layer.”
CompAct (2019, background): “To mitigate these issues, there is growing interest in the design of hardware accelerators to speed-up CNN inference from both industry and academia [4, 5, 9, 17, 27, 30].”
Fathom: reference workloads for modern deep learning methods (2016, neutral): “Category Feature [8] [9] [10] [11] [12] [14] [21] [24] [26] [35] [38] [39] [40] [44] [47] [49] Fathom”
Recent Advances in Convolutional Neural Network Acceleration (2018, methodology): “35 GHz C870, and a 200 MHz FPGA, the proposed design achieves a 4× to 8× speed boost [125].”
Maximizing CNN accelerator efficiency through resource partitioning (2016, methodology): “For example, the 2D-convolvers used in [3, 10, 12, 22] must be provisioned for the largest filter across layers; they will necessarily be underutilized when computing layers with smaller filters.”