Cryptanalysis of DES Implemented on Computers with Cache
By Y. Tsunoo, Teruo Saito, Tomoyasu Suzaki, Maki Shigeri, Hiroshi Miyauchi. Workshop on Cryptographic Hardware and Embedded Systems, 2003
302 citations recorded by the source corpus.
Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition
View Paper: https://www.semanticscholar.org/paper/c569925bc8972c2c8a640a57513de6c904981d54
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Artificial Intelligence
- Daniel Gruss
- Stefan Mangard
- Yuval Yarom
- Clémentine Maurice
- Michael Schwarz
- Moritz Lipp
- Daniel Genkin
- Thomas Eisenbarth
In Computer Vision and Pattern Recognition
Citations in the corpus
- Covert and Side Channels Due to Processor Architecture (2006, background): “Cache-based side channel attacks were studied in [26-27].”
- Faster and Timing-Attack Resistant AES-GCM (2009, background): “demonstrated the practical feasibility of cache-timing attacks against symmetric-key ciphers MISTY1 [33] and DES [32], and were the first to mention an attack against AES (without giving further details).”
- ARMageddon: Cache Attacks on Mobile Devices (2015, methodology): “Initially, cache timing attacks were performed on cryptographic algorithms [10, 31, 32, 41, 42, 45, 56].”
- Side-Channel Attacks: Ten Years After Its Publication and the Impacts on Cryptographic Module Security Testing (2005, methodology): “This is usually classified as a side-channel attack on software-implemented ciphers, and it has already broken MISTY1 ([44]), DES, AES and Camellia [43] et al.”
- New cache designs for thwarting software cache-based side channel attacks (2007, background): “studied attacks against DES on computers with caches [15][16].”
- Cache Template Attacks: Automating Attacks on Inclusive Last-Level Caches (2015, background): “Later on, practical attacks for DES were proposed by Page [42] as well as Tsunoo et al. [51].”
- Cache Attacks and Countermeasures: The Case of AES (2006, background): “In 2003, Tsunoo et al. [ 13 ] described attacks using timing eects due to collisions in the memory lookups inside the cipher, as opposed to the cipher-attacker collisions we investigate.”
- HomeAlone: Co-residency Detection in the Cloud via Side-Channel Analysis (2011, unknown): “, [43], [42], [35], [8], [5], [15], [33], [34], [44], [23], [40], [25], [30], [16], [37], [49], [14], [24],”
- Wait a Minute! A fast, Cross-VM Attack on AES (2014, background): “[27] investigated timing side channel attacks due to internal table look up operations in the cipher that affect the cache behavior.”
- Efficient Cache Attacks on AES, and Countermeasures (2010, methodology): “devised a timing-based attack on MISTY1 [57,58] and DES [56], exploiting the effects of collisions between the various memory lookups invoked internally by the cipher (as opposed to the cipher vs.”
- CacheZoom: How SGX Amplifies The Power of Cache Attacks (2017, unknown): “Symmetric keys can be generated at runtime from a secure random entropy (using RDRAND instruction) and/or transferred through a public secure channel without the attacker knowledge.”
- S$A: A Shared Cache Attack That Works across Cores and Defies VM Sandboxing -- and Its Application to AES (2015, background): “As explained in Section II, a user does not use the physical memory directly.”