Cache Attacks and Countermeasures: The Case of AES

By Dag Arne Osvik, Adi Shamir, Eran Tromer. The Cryptographer's Track at RSA Conference, 2006

1,660 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/78f5ffc64833b1d166a3555c0b8c763b2684058c

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In Artificial Intelligence

Citations in the corpus

Post-Quantum Key Exchange for the TLS Protocol from the Ring Learning with Errors Problem (2015, background): “Attacks which use this type of information are known as cacheattacks [37].”
Packet Chasing: Spying on Network Packets over a Cache Side-Channel (2019, neutral): “2 [22, 35] Error Rate (%) 9.”
Raccoon: Closing Digital Side-Channels through Obfuscated Execution (2015, methodology): “Side-channel attacks have been used to break AES [26] and RSA [27] encryption schemes, to break the Difﬁe-Hellman key exchange [15], to ﬁngerprint software libraries [46], and to reverse-engineer commercial processors [18].”
Telling Your Secrets without Page Faults: Stealthy Page Table-Based Attacks on Enclaved Execution (2017, background): “In a more general, non-PMA context, there exists a vast amount of research on microarchitectural cache timing vulnerabilities [35, 50, 17].”
On the power of simple branch prediction analysis (2007, methodology): “With the advent of the papers from [26, 27, 30] a new and very interesting attack paradigm was initiated.”
Real time detection of cache-based side-channel attacks using hardware performance counters (2016, neutral): “In [6] Osvik et al.”
Side-Channel Attacks: Ten Years After Its Publication and the Impacts on Cryptographic Module Security Testing (2005, background): “A number of countermeasures to mitigate the cached-based attacks have been proposed, to name a few, to remove cache or cached S-box access, to disable cache flushing, to perform time and miss skewings, to use application-specific algorithmic masking, to depend on operating system support, to adopt p”
Yet another MicroArchitectural Attack:: exploiting I-Cache (2007, methodology): “, a cipher process, running in parallel on the same processor as done in [29, 24, 32].”
Leaky Cauldron on the Dark Land: Understanding Memory Side-Channel Hazards in SGX (2017, neutral): “, access driven attacks [17]) have been demonstrated on x86 architectures, including data caches (and also per-core L2 unified caches) [31], [30], [28], [36], [17], [18], instruction caches [8], [9], [43], and inclusive LLCs [41], [40], [12], [44], [22], [27], [20], [16], [29], [19], [23], [26], [42”
CacheZoom: How SGX Amplifies The Power of Cache Attacks (2017, background): “We explain how to establish a high resolution channel on a compromised OS to monitor an SGX enclave.”
A Systematic Evaluation of Transient Execution Attacks and Defenses (2018, background): “However, these latency differences can be exploited in side-channels and covert channels [53, 70, 95, 29, 63].”
S$A: A Shared Cache Attack That Works across Cores and Defies VM Sandboxing -- and Its Application to AES (2015, background): “[2].”
Malware Guard Extension: Using SGX to Conceal Cache Attacks (2017, methodology): “Prime+Probe is a cache attack technique that has ﬁrst been used by Osvik et al. [16].”
Efficient Cache Attacks on AES, and Countermeasures (2010, methodology): “An abridged version of this paper was published in [45], and announced in [44].”
The Security Impact of a New Cryptographic Library (2012, neutral): “See [31] and [39].”