New cache designs for thwarting software cache-based side channel attacks

By Zhenghong Wang, Ruby B. Lee. International Symposium on Computer Architecture, 2007

642 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Signal Processing

View Paper: https://www.semanticscholar.org/paper/08dcda95dcbd1ebe906a1c24507b7814759462aa

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Citations in the corpus

S$A: A Shared Cache Attack That Works across Cores and Defies VM Sandboxing -- and Its Application to AES (2015, methodology): “Private L3 Cache Slices: One way to avoid the cache leakage that S$A uses is to make the cache slices private per VM, similar to the countermeasure suggested in [50].”
Detecting Privileged Side-Channel Attacks in Shielded Execution with Déjà Vu (2017, background): “Modifying the processor architecture [50, 36, 15, 32] and relying on system-level isolation enhancement [49, 27, 29, 60, 48, 57] are not possible in the settings we consider.”
Sealed-Glass Proofs: Using Transparent Enclaves to Prove and Sell Knowledge (2017, background): “Additional software or physical side-channels [4]–[8] could further compromise an enclave’s secrets.”
BranchScope: A New Side-Channel Attack on Directional Branch Predictor (2018, methodology): “This solution is similar to randomizing the mapping of caches as a protection against side-channel attacks [52].”
Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures (2018, background): “Further, there are proposals for security-oriented cache mechanisms such as PLCache [45], Random Fill Cache [46], SHARP [47] and SecDCP [48].”
HomeAlone: Co-residency Detection in the Cloud via Side-Channel Analysis (2011, neutral): “First, they include new cache designs (e.g., [46], [ 47 ], [26], [28], [48]).”
Packet Chasing: Spying on Network Packets over a Cache Side-Channel (2019, neutral): “These mitigation strategies include identifying the leakage in software [48], observing anamalous cache behavior [49], [56], closing channels at hardware design time [41]–[45], dynamic cache partitioning [45], [46], [50], strictly reserving physical cores to security-sensitive threads [51], randomiz”
A survey of microarchitectural timing attacks and countermeasures on contemporary hardware (2016, methodology): “Wang and Lee [158] suggested an alternative approach, described as a partition-locked cache (PLcache).”
High-Resolution Side Channels for Untrusted Operating Systems (2017, background): “Cache side channels have been known for a long time, and a variety of defenses has been designed against them [15, 17, 19, 21, 32, 43, 47], working at the hardware, hypervisor, OS or compiler level.”
SgxPectre Attacks: Leaking Enclave Secrets via Speculative Execution (2018, background): “ode. Side-channel defenses. Existing countermeasures to side-channel attacks can be categorized into three classes: hardware solutions, system solutions, and application solutions. Hardware solutions [76, 77, 21, 47, 45, 18]requiremodiﬁcationoftheprocessors,whicharetypically effective, but are limit”
DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors (2018, methodology): “RPcache [33], [56] trusts the OS to assign different hardware process IDs to mutually mistrusting entities, and its mechanism does not directly scale to large LLCs.”
SgxPectre: Stealing Intel Secrets from SGX Enclaves Via Speculative Execution (2018, background): “Hardware solutions [86], [87], [15], [53], [51], [12] require modification of the processors, which are typically effective, but are limited in that the time window required to have”
Sanctum: Minimal Hardware Extensions for Strong Software Isolation (2016, background): “PLcache [31, 51] and the Random Fill Cache Architecture (RFill, [38]) were designed and analyzed in the context of a small region of sensitive data, and scaling them to protect a potentially large enclave without compromising performance is not straightforward.”