A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation

By Kris Tiri, Ingrid M. R. Verbauwhede. Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004

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Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches (2011, background): “Circuit design approaches [36,37] try to remove the root of the side-channel leakage by balancing the power consumption of different data values.”
Aegis: A Single-Chip Secure Processor (2007, background): “As power analysis has become one of the major security concerns for small devices such as smartcards, various protection techniques have been proposed [24, 79, 103, 123, 138, 139, 140].”
Side-Channel Leakage of Masked CMOS Gates (2005, background): “styles with a data-independent power consumption [20, 21], noise generators and the insertion of random delays [4, 12].”
Introduction to differential power analysis (2011, background): “Several works have focused on dual-rail precharge logic [58–63].”
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints (2005, methodology): “of this kind are SABL [18,19], WDDL [20], and Dual-Spacer DRP [16].”