Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints

By Thomas Popp, Stefan Mangard. Workshop on Cryptographic Hardware and Embedded Systems, 2005

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Pushing the Limits: A Very Compact and a Threshold Implementation of AES (2011, background): “Amongst the countermeasures proposed at different levels of design and abstraction Masking methods, which rely on randomizing key-dependent intermediate values processed during the execution of the cipher, are widely applied on either the algorithmic level [26] or the cell level [27].”
Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches (2011, background): “For instance, in [27], the authors report an increase in area with a factor 5, for a decrease in performance with factor 0.”
Successfully Attacking Masked AES Hardware Implementations (2005, background): “Glitches should either be completely avoided [13] or the used masking scheme needs to be adapted in a way that it also works in the presence of glitches [5].”
Threshold Implementations Against Side-Channel Attacks and Glitches (2006, background): “Gate-level solutions are proposed in [9, 20].”