CMOS design near the limit of scaling

By Yuan Taur. 2002

410 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/b75102366caebc9cbb1f341ec1e67d95eb31348e

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In Electrical and Electronic Engineering

1. Bram Nauta
2. S. Thompson

Citations in the corpus

• Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology (2008, neutral): “an associated increase in quiescent power [18].”
• Analog circuits in ultra-deep-submicron CMOS (2005, background): “While this evolution in CMOS technology is by definition very beneficial for digital, this is not so for analog circuits [1]–[3].”
• In search of "Forever," continued transistor scaling one new material at a time (2005, background): “since it is scalable to future logic technology generations, can be integrated at low cost, and is additive with nearly all past transistor enhancement changes like halo implants, retrograde wells, super halos [31], offset spacers [39], and abrupt source”
• Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs (2009, background): “With the application of high-k dielectric and a novel doping profile, the scaling limit for planar MOSFET is extended to ∼20 nm (68).”