A technique to build a secret key in integrated circuits for identification and authentication applications

By Jae W. Lee, D. Lim, Blaise Gassend, Ed Suh, Marten van Dijk, Srini Devadas. 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525), 2004

877 citations recorded by the source corpus.

Subfields: Cellular and Molecular Neuroscience, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/aff0b4712c5f8b82635ec022a6803a5de6348c6f

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Citations in the corpus

PUF Modeling Attacks on Simulated and Silicon Data (2013, methodology): “(2) From the different optimization methods which we tested in our ML experiments (standard gradient descent, iterative reweighted least squares, RProp [2], [35]), RProp gradient descent performed best.”
Aegis: A Single-Chip Secure Processor (2007, methodology): “While PUFs can be implemented with various physical systems, we use silicon PUFs (SPUFs) that are based on the hidden timing and delay information of integrated circuits [4], [9].”
Security analysis of integrated circuit camouflaging (2013, background): “Physical unclonable functions are leveraged to produce such IDs [37, 38].”
Modeling attacks on physical unclonable functions (2010, methodology): “Most electrical Strong PUFs further operate at frequencies of a few MHz [12].”
Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain (2014, neutral): “[66] J.”
Active Hardware Metering for Intellectual Property Protection and Security (2007, background): “A team of researchers has explored the idea of using variability-induced delays for authentication and security [9, 19, 29].”
Design and Implementation of PUF-Based "Unclonable" RFID ICs for Anti-Counterfeiting and Security Applications (2008, background): “While PUFs can be implemented with various physical systems, this paper focuses on silicon PUFs that are based on the hidden timing and delay information of integrated circuits [4] [5].”
A PUF taxonomy (2019, methodology): “12 Name Mechanism Parameter Implicity Evaluation Family Arbiter PUF [1] AllElectronic Time Implicit Intrinsic Racetrack ClockPUF [43] Ring Oscillator PUF [44] Frequency TERO PUF [45] Transient/ Glitch GlitchPUF [31] Voltage/ Current SRAM failure PUF [32] Volatile memory Bistable Ring PUF [46] Bistab”
Physically Unclonable Functions (2012, background): “[80] that their basic arbiter PUF can indeed be easily modeled and they even present modeling attack results for their own implementation.”
Physical Unclonable Functions for Device Authentication and Secret Key Generation (2007, background): “Section 7), this paper focuses on silicon PUFs (SPUFs) that are based on the hidden timing and delay information of integrated circuits [6, 7].”
Lightweight secure PUFs (2008, background): “From one viewpoint, embedded systems are often under strict power, cost, and size constraints and, therefore, must employ only light-weight security protocols.”