DRAMsim: a memory system simulator

By David T. Wang, B. Ganesh, Nuengwong Tuaycharoen, K. Baynes, Aamer Jaleel, Bruce L. Jacob. CARN, 2005

359 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/a8887bd8c006f7b83aa4db8b8e49e70fc4d24043

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Citations in the corpus

Page placement in hybrid memory systems (2011, background): “The table shows power parameters [20] of DRAM and PCM chips, and the timing parameters that change across memory technologies [20, 28, 37] (although we simulate all relevant parameters [22, 32]).”
DRAMSim2: A Cycle Accurate Memory System Simulator (2011, background): “One of the first attempts to provide a detailed model of main memory was DRAMSim [1], software designed to explore memory systems concepts by providing models for many types of memory systems (such as SDRAM, DDR, and FBDIMM).”
The gem5 Simulator: Version 20.0+ (2020, methodology): “For instance, gem5 has been integrated with the Structural Simulation Toolkit (SST) [35, 62], which uses gem5’s detailed CPU models in conjunction with SST’s multi-node modeling capabilities. DRAMSim [48, 64, 76] which provides cycle-accurate DRAM models has also been integrated with gem5. Additiona”
CACTI 7 (2017, methodology): “Memory simulators such as DRAMSim [Wang et al. 2005], USIMM [Chatterjee et al. 2012], and Ramulator [Kim et al. 2015] are performance simulators that model DRAM timing in a cycle-accurate manner.”
Reducing memory interference in multicore systems via application-aware memory channel partitioning (2011, methodology): “The memory model is based on DDR2 timing parameters [14], verified using DRAMSim [27].”
Evaluating STT-RAM as an energy-efficient main memory alternative (2013, methodology): “The memory model in the simulator is verified using DRAMSim [60] and its parameters are set to DDR3 memory timing parameters [41].”
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior (2010, methodology): “The memory subsystem is modeled using DDR2 timing parameters [10], which were verified using DRAMSim [23] and measurements from real hardware.”
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors (2007, neutral): “The DRAM memory system model and the performance model are loosely based on DRAMsim [31] and Intel Pentium M [9], respectively.”