The torus routing chip

By William (Bill) J. Dally, C. Seitz. Distributed computing, 2005

466 citations recorded by the source corpus.

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

Achieving single channel, full duplex wireless communication (2010, methodology): “This idea is similar to wormhole switching [7] used for multihop wired communication networks.”
Energy- and performance-aware mapping for regular NoC architectures (2005, background): “Because of the limited buffering resources available and the stringent latency requirements for typical NoC applications, we believe that wormhole-based routing [3] is the most appropriate routing technique for NoCs.”
Performance evaluation and design trade-offs for network-on-chip interconnect architectures (2005, unknown): “1d [28].”
A case for bufferless routing in on-chip networks (2009, background): “Compared to wormhole routing [11] in traditional, buffered baseline routing algorithms, flit-level switching in FLIT-BLESS has three potential disadvantages.”
DyAD - smart routing for networks-on-chip (2004, background): “switching [2] to provide higher achievable throughput values compared to wormhole switching alone, while reducing the buffer space required at the intermediate nodes when compared to virtual cutthrough.”
QNoC: QoS architecture and design process for network on chip (2004, methodology): “IDT: Network on chip; QoS architecture; Wormhole switching; QNoC design process; QNoC”