The design and implementation of a first-generation CELL processor

By D. Pham, Shigehiro Asano, M. Bolliger, M. N. Day, H. Peter Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi and 10 more. ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005., 2005

605 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/a67ed2621fddd692aa7527e1fd67670b6eeadbd5

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Citations in the corpus

Silicon-photonic clos networks for global on-chip communication (2009, background): “The electrical on-chip networks used in today’s multicore systems (e.g., crossbars [8], meshes [3], and rings [ 11 ]) will either be difficult to scale to higher core counts with reasonable power and area overheads or introduce significant bandwidth and latency non-uniformities.”
Larrabee: a many-core x86 architecture for visual computing (2008, methodology): “The IBM Cell * was designed with these high throughput workloads in mind [Pham et al. 2005].”
Power efficient processor architecture and the cell processor (2005, background): “Figure 1 shows the organization of the first-generation Cell processor [5].”
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors (2008, background): “At the chip scale, the trend toward multicore architectures and chip multiprocessors (CMPs) for driving performance-per-watt by increasing the number of parallel computational cores is dominating new commercial releases [2], [3], [4], [5], [6].”
The potential of the cell processor for scientific computing (2005, methodology): “Cell Background Cell [1, 2] was designed by a partnership of Sony, Toshiba, and IBM (STI) to be the heart of Sony’s forthcoming PlayStation3 gaming system.”
Thousand Core ChipsA Technology Perspective (2007, background): “The net work can be a ring [ 3 ] or a higher dimensional network such as a mesh [4] to reduce latency.”
Parallel Implementation for 3-D CT Image Reconstruction on Cell Broadband Engine (2007, background): “consists of two different types of processor elements, a PowerPC Processor Element (PPE) and Synergistic Processor Elements (SPEs) [10].”
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration (2009, background): “[4] S. Bhat, Energy Models for Network-on-Chip Components , M.S. Thesis, Dept. of Mathematics and Computer Science, Royal Institute of Technology, Eindhoven, 2005.”
Analyzing CUDA workloads using a detailed GPU simulator (2009, methodology): “The Cell processor [7, 38] is a hardware architecture that can function like a stream processor with appropriate software support.”
Qilin: Exploiting parallelism on heterogeneous multiprocessors with adaptive mapping (2009, background): “Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.”
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor (2006, background): “THE architectural vision of “bringing supercomputer power to everyday life” is the driving force behind the Cell processor design, setting a new performance standard by exploiting parallelism while achieving high frequency [1].”
Silicon Photonics (2006, methodology): “The eight-core processor has an internal computation power of 256 giga floating point operations per second (GFLOPS) and communicates with the peripheral graphics processor and memory at data rates of 25 Gb/s or higher [16], [17].”