Silicon-photonic clos networks for global on-chip communication
By A. Joshi, C. Batten, Yong-jin Kwon, Scott Beamer, I. Shamim, Krste Asanovic, Vladimir Marko Stojanovic. 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009
343 citations recorded by the source corpus.
Future manycore processors will require energy-efficient, high-throughput on-chip networks. Silicon-photonics is a promising new interconnect technology which offers lower power, higher bandwidth density, and shorter latencies than electrical interconnects. In this paper we explore using photonics to implement low-diameter non-blocking crossbar and Clos networks. We use analytical modeling to show that a 64-tile photonic Clos network consumes significantly less optical power, thermal tuning power, and area compared to global photonic crossbars over a range of photonic device parameters. Compared to various electrical on-chip networks, our simulation results indicate that a photonic Clos network can provide more uniform latency and throughput across a range of traffic patterns while consuming less power. These properties will help simplify parallel programming by allowing the programmer to ignore network topology during optimization.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/a1344c419edfd21148d4415e7296fc4996270272
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In Electrical and Electronic Engineering
Citations in the corpus
- DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling (2012, background): “Whereas there has been significant prior work on electronic NoC modeling (see Section II-C), evaluations of photonic NoC architectures have not yet evolved past the use of fixed energy costs for photonic devices and interface circuitry [1] [3] [4] [5], whose values also vary from study to study.”