Junctionless nanowire transistor (JNT): Properties and design guidelines

By J. Colinge, A. Kranti, Ran Yan, Carter Lee, Isabelle Ferain, R. Yu, N. Akhavan, P. Razavi. 2010 Proceedings of the European Solid State Device Research Conference, 2010

581 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/a6291e1ea1f80da010d63079711e3521ad2266b1

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Citations in the corpus

Junctionless Tunnel Field Effect Transistor (2013, background): “Also, as this device does not require any metallurgical junction, it should be simpler to fabricate, have better electrical properties, and less variability than MOSFET [3]–[5].”
A Full-Range Drain Current Model for Double-Gate Junctionless Transistors (2011, methodology): “The proposed model does not use fitting parameters, and it captures the phenomenon of the bulk conduction mechanism [2] in all regions of device operation.”
Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors (2011, background): “Moreover, the observed VT fluctuation is less sensitive than those predicted by simulation because of the nature of the GAA structure [12].”
Junctionless Multiple-Gate Transistors for Analog Applications (2011, background): “starts to operate in accumulation just after the threshold [12].”
Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling (2011, background): “A recent proposal for a bulk junctionless device [7] solves some”
Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors (2011, background): “However, the surface current flows at a gate voltage that is much higher than the threshold voltage for the bulk current [8].”
Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor With High- $\kappa$ Spacers (2011, result): “Similar to the case of conventional MOSFETs, where JLTs suffer from SCEs, scaling the gate oxide thickness and reducing the device layer thickness are some of the methods to supress SCEs [6].”
Effect of Band-to-Band Tunneling on Junctionless Transistors (2012, background): “New JLT designs include nanowire gate-all-around (GAA) architectures [4], [8], trigated nanowire architectures with a silicon-on-insulator (SOI) [1], and bulk substrates [5].”