Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor With High- $\kappa$ Spacers
By Suresh Gundapaneni, S. Ganguly, Anil Kottantharayil. IEEE Electron Device Letters, 2011
151 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/9d2faec4f2e403eec79e298f288be6ef63b80206
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In Electrical and Electronic Engineering
- Suresh Gundapaneni
- Anil Kottantharayil
- S. Ganguly
- Kota Murali
- Mohit Bajaj
- R. Pandey
- Roy P. Paily
- Ratul Kumar Baruah
Citations in the corpus
- A Dual-Material Gate Junctionless Transistor With High- $k$ Spacer for Enhanced Analog Performance (2014, background): “55 V), output conductance is governed by channel length modulation (CLM) and at higher VDS, it is governed by drain-induced barrier lowering (DIBL), if impact ionization is not considered [11].”
- Effect of Band-to-Band Tunneling on Junctionless Transistors (2012, methodology): “designs, based on Lilienfeld’s first transistor architecture [2], which does not have any metallurgical junctions, have been proposed [3]–[7] and successfully fabricated in silicon [1],”