Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling
By Suresh Gundapaneni, S. Ganguly, Anil Kottantharayil. IEEE Electron Device Letters, 2011
238 citations recorded by the source corpus.
Subfields: Biomedical Engineering, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/d375392c2c0604a9819059ae28e1b039e615df31
How researchers see this paper
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In Biomedical Engineering
In Electrical and Electronic Engineering
- Suresh Gundapaneni
- Anil Kottantharayil
- S. Ganguly
- Kota Murali
- Mohit Bajaj
- R. Pandey
- Juan Pablo Duarte
- Sung-Jin Choi
Citations in the corpus
- Effect of Band-to-Band Tunneling on Junctionless Transistors (2012, methodology): “The models used for the simulations are calibrated against a long-channel experimentally demonstrated JLT, as described in [6].”
- Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor With High- $\kappa$ Spacers (2011, methodology): “device simulated are well calibrated with experimental JLT data from [2] and were listed in our previous work [5].”
- A Full-Range Drain Current Model for Double-Gate Junctionless Transistors (2011, background): “2169266 also difficult to obtain under such a condition [3].”