NROM: A novel localized trapping, 2-bit nonvolatile memory cell

By B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, D. Finzi. IEEE Electron Device Letters, 2000

588 citations recorded by the source corpus.

This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal /spl sim/400 electrons above a n/sup +//p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The new read methodology is very sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability. The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250/spl deg/C, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 /spl mu/m process, the area of a bit is 0.315 /spl mu/m/sup 2/ and 0.188 /spl mu/m/sup 2/ in 0.25 /spl mu/m technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/a37b0869b08199d38e20553a0df429bdbf3f35ae

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Citations in the corpus

Introduction to flash memory (2003, background): “The problem can be solved exploiting different physical effects [11].”
Metal nanocrystal memories-part II: electrical characteristics (2002, background): “ANOCRYSTAL memories and MNOS (SONOS) memory devices employing discrete charge traps as storage elements have exhibited great potential in device performance, power consumption, and technology scalability, thus recently attracting much research attention as promising candidates to replace the convent”
Metal nanocrystal memories. I. Device design and fabrication (2002, background): “Moreover, the discreteness of the charge traps enables multibit-per-cell storage [ 5 ], [6] without going through the multilevel approach, which poses stringent requirement on the control of threshold spread [7].”
Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices (2001, background): “In these devices, the storage medium consists either of natural nitride traps [1]‐[ 3 ], or semiconductor nano-crystals fabricated by different techniques (Si nano-dot self-assembled by chemical vapor deposition (CVD) [4], by low-pressure CVD [5]‐[7], or by annealing of silicon rich oxide [8], Sn an”
Present and Future Non-Volatile Memories for Space (2010, background): “25 shows the programming window (the difference between the programmed and erased levels) for an NROM cell [126].”