Extension and source/drain design for high-performance FinFET devices

By J. Kedzierski, M. Ieong, Edward J. Nowak, T. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, H.-S.P. Wong. 2003

237 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/8f72a3f5bc7ed564049a453efc1350725f872712

How researchers see this paper

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In Electrical and Electronic Engineering

1. Vishal P. Trivedi
2. Jerry G. Fossum
3. A. Dixit

Citations in the corpus

• Nanoscale FinFETs with gate-source/drain underlap (2005, background): “This seems to be the most viable approach to doping the SDEs as direct ion implantation into the thin fins would require high tilt angle and low energy [15], followed by relatively high-temperature and fast, rapid-thermal anneal to prevent S-D punch-through.”
• Analysis of the parasitic S/D resistance in multiple-gate FETs (2005, background): “An SEG of Si on the HDD regions has been reported as a technology solution for this [16].”
• The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance (2005, background): “First is the tied double-gate, sidewall conduction structure [60]–[71].”