A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking

By Jie Deng, H. Philip Wong. IEEE Transactions on Electron Devices, 2007

785 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Materials Chemistry

View Paper: https://www.semanticscholar.org/paper/b46ebb916faa28f0d81fadf25975f6b345b82b34

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Fabrizio Lombardi
2. Yong-Bin Kim
3. Sheng Lin
4. H. Philip Wong
5. Jie Deng
6. Chongwu Zhou
7. Nishant Patil
8. Daniele Ielmini

In Materials Chemistry

1. Fabrizio Lombardi
2. Yong-Bin Kim
3. Sheng Lin
4. H. Philip Wong
5. Jie Deng
6. Chongwu Zhou

Citations in the corpus

• A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region (2007, methodology): “We will show in [1] that this optimistic performance advantage is not achievable in a practical device structure and will be significantly degraded by the device/circuit nonidealities, including the series resistance of doped source/drain region, the SB resistance at the metal/CNT interface, the gat”
• Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes (2009, background): “cuits, multiple CNTs are needed per CNFET to provide the current density necessary for high-performance digital circuits [2]–[4].”
• CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits (2011, methodology): “This HSPICE model of the CNTFET is described in more detail in [15] and [16].”