Principles and Practices of Interconnection Networks

By Download Here. 2004

1,905 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/850225c7c13b4cffa2ee101798f488dfa289ee3e

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Citations in the corpus

Survey of Fog Computing: Fundamental, Network Applications, and Research Challenges (2018, background): “ogy [60], which is one of the widely used switch-centric”
A detailed and flexible cycle-accurate Network-on-Chip simulator (2013, methodology): “The original simulator (BookSim1) was released as part of an interconnection network textbook by Dally and Towles [1] and was used to generate the performance graphs in the textbook.”
Data Center Networks (2013, unknown): “Flexible topologies such as c-Through [14], Helios [7] and OSA [6] enable reconfiguration of their network topology at run time based on the traffic demand.”
Data Center Network Virtualization: A Survey (2013, background): “Clos topology is a topology built up from multiple stages of switches [10].”
CACTI 6.0: A Tool to Model Large Caches (2009, background): “There have been a number of router proposals in the literatur with different levels of speculation and pipeline stages [4, 8, 11].”
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 (2007, background): “As discussed earlier, various routers have been proposed with differing levels of speculation and pipeline stages [13, 26, 28].”
Slim Fly: A Cost Effective Low-Diameter Network Topology (2014, unknown): “According to [10], we define the accepted bandwidth as the offered load of random uniform traffic which saturates the network.”
Neural Shufﬂe-Exchange Networks − Sequence Processing in O( n log n ) Time (2019, methodology): “This architecture is derived from the Shufﬂe-Exchange network used for packet routing in the ﬁeld of computer networks (Dally and Towles, 2004).”
Technology-Driven, Highly-Scalable Dragonfly Topology (2008, background): “The topology of an interconnection network largely determines both the performance and the cost of the network [8].”
On the Design of a Photonic Network-on-Chip (2007, unknown): “When dimension order routing is used, no channeldependency cycles are formed between dimensions, so deadlock involving messages traveling in different dimensions cannot occur [7].”
DaDianNao: A Machine-Learning Supercomputer (2014, unknown): “0 interconnection network simulator [10] (Orion2.”
Firefly: illuminating future network-on-chip with nanophotonics (2009, methodology): “The simulator models both a 4-stage pipelined router [11, 37] and an aggressive, single-cycle router [27].”
A case for bufferless routing in on-chip networks (2009, methodology): “Circuit switching [12] can also remove/reduce buffering requirements but it comes at the cost of connection setup/teardown overheads that are not present in our proposal.”
Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations (2014, unknown): “, one-to-one routing), meshes are provably deadlock-free when dimension-order routing or virtual channels are used [43].”
Noxim: An open, extensible and cycle-accurate network on chip simulator (2015, unknown): “These are strictly related to the tasks that are performed in each tile and Noxim provides several commonly used data traffic models which abstract typical communication patterns [3].”
VL2: a scalable and flexible data center network (2009, methodology): “VL2 consists of a network built from low-cost switch ASICs arranged into a Clos topology [ 7 ] that provides extensive path diversity between servers.”