McRT-STM: a high performance software transactional memory system for a multi-core runtime

By Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hudson, Chi Cao Minh, Ben Hertzberg. ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming, 2006

528 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/216ca5dbd43d7b7d6d3a2d6087932e230052854e

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Citations in the corpus

STAMP: Stanford Transactional Applications for Multi-Processing (2008, background): “Similarly, it is commonly thought that eager systems should perform better than lazy systems as eager systems perform their memory updates throughout the transaction, instead of waiting till the transaction commit point [29, 34].”
Dynamic performance tuning of word-based software transactional memory (2008, methodology): “T INY STM shares many properties with other word-based STMs: in particular with TL2 (several aspects of our STM library were directly inspired by TL2’s reference implementation) but also with Ennals’ [4] and Saha et al. ’s [13, 16] designs.”
Transactional memory (2010, methodology): “McRT-STM [89] is a software transactional memory system for C++ and Java implemented on top of the McRT [90] run-time system.”
Transactional Locking II (2006, methodology): “Another option is to perform periodic validations, for example, once every number of transactional loads or when looping in the user code [ 11 ].”
Transactional Memory, 2nd edition (2010, background): “[274] examine the trade offs between these approaches, and Spear et al.”
An effective hybrid transactional memory system with strong isolation guarantees (2007, methodology): “STM systems implement all bookkeeping in software using instrumentation code (read and write barriers) and software data structures [14, 22, 11, 15].”