Sub-20 nm CMOS FinFET technologies

By Yang-Kyu Choi, N. Lindert, Peiqi Xuan, Stephen Tang, Daewon Ha, E. Anderson, Tsu-Jae King, J. Bokor, Chenming Calvin Hu. International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001

225 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/74e43b38a252cac7af359b294604d7775960d17d

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In Electrical and Electronic Engineering

1. Shiying Xiong
2. Jeffrey Bokor

Citations in the corpus

• Extension and source/drain design for high-performance FinFET devices (2003, unknown): “From several double-gate device architectures the FinFET [2]‐[ 5 ] has emerged as a promising device structure.”
• Impact of Line-Edge Roughness on FinFET Matching Performance (2007, result): “proposed, which is based on the use of dummy spacers and achieves higher fin density as compared to RDF [9].”
• Sensitivity of double-gate and FinFETDevices to process variations (2003, background): “The large parasitic resistance between the channel and source/drain (S/D)is another challenge to the performance of FinFET devices [ 4 ].”