Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling

By Greg Semeraro, G. Magklis, Rajeev Balasubramonian, D. Albonesi, Sandhya Dwarkadas, Michael Lee Scott. Proceedings Eighth International Symposium on High Performance Computer Architecture, 2002

405 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/4bac34db99b0cb23a6da11c43486165e6a9f17d4

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Citations in the corpus

System level analysis of fast, per-core DVFS using on-chip switching regulators (2008, background): “Dynamic voltage and frequency scaling (DVFS) was introduced in the 90's [19], offering great promise to dramatically reduce power consumption in large digital systems by adapting both voltage and frequency of the system with respect to changing workloads [16] [28] [30] [36].”
Energy Efficient Resource Management in Virtualized Cloud Data Centers (2010, neutral): “A number of practices can be applied to achieve energy-efﬁciency, such as improvement of applications’ algorithms, energy efﬁcient hardware, Dynamic Voltage and Frequency Scaling (DVFS) [13], terminal servers and thin clients, and virtualization of computer resources [1].”
Temperature-aware microarchitecture: Modeling and implementation (2004, background): “A processor must typically stall for anywhere from 10 50 µs to accommodate resynchronization of the clock s phase-locked loop (PLL), but if the transition is gradual enough, the processor can execute through the change without stalling, as the Xscale is believed to do [Semeraro et al. 2002].”
Temperature-aware microarchitecture (2003, background): “For each change in setting, DVS schemes must stall for anywhere from 10–50 s to accommodate resynchronization of the clock’s phase-locked loop (PLL), but if the transition is gr adual enough, the processor can execute through the change withou t stalling, as the Xscale is believed to do [23].”
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget (2006, background): “However, this should be considered as an optimistic bound since the supply voltages are shrinked more aggressively in emerging processor generations [38].”
Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction (2003, methodology): “Fine-grained voltage/frequency scaling techniques using multiple clock domains have been proposed recently [21, 34] which obviate some of the disadvantages of conventional scaling-based techniques discussed elsewhere in this paper.”