Characterizing flash memory: Anomalies, observations, and applications
By Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, Steven Swanson, Eitan Yaakobi, Paul H. Siegel, J. Wolf. Micro, 2009
502 citations recorded by the source corpus.
Subfields: Computer Networks and Communications
View Paper: https://www.semanticscholar.org/paper/2c8734220a9015910515d5b98587197448604a24
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In Computer Networks and Communications
Citations in the corpus
- Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives (2017, background): “Program interference refers to the phenomenon where the programming of a flash cell induces errors on adjacent flash cells within a flash block [18, 26, 44, 56, 108].”
- PebblesDB: Building Key-Value Stores using Fragmented Log-Structured Merge Trees (2017, background): “High write amplification increases the load on storage devices such as SSDs, which have limited write cycles before the bit error rate becomes unacceptable [3, 26, 39].”
- Essential roles of exploiting internal parallelism of flash memory based solid state drives in high-speed data processing (2011, unknown): “[3, 5–7, 10, 14, 27, 30]).”
- Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors (2014, background): “Disturbance errors are a general class of reliability problem that a✏icts not only DRAM, but also other memory and storage technologies: SRAM [16, 26, 40], flash [10, 12, 13, 19, 25], and hard-disk [36, 63, 68].”
- CAFTL: A Content-Aware Flash Translation Layer Enhancing the Lifespan of Flash Memory based Solid State Drives (2011, background): “[22] have presented an empirical study on the performance, power, and reliability of flash memories.”
- Performance impact and interplay of SSD parallelism through advanced commands, allocation strategy and data granularity (2011, background): “…and Flash Translation Layer (FTL), from performance to endurance and energy efficiency, have been extensively studied in the literature, the SSD being studied was by and large treated as a grey or black box in that many of the internal features such as advanced commands, physical-page…”
- SSD Failures in Datacenters: What? When? and Why? (2016, methodology): “Bit Error Rate (BER) (as in [15, 24]) is another standard metric used to capture the rate at which such errors occur, relative to the total data read by the device.”
- NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory (2012, background): “[40] reported both latency and power consumption measurements of several commercial NAND Flash chips from different vendors.”
- The bleak future of NAND flash memory (2012, methodology): “For SSD designers, this performance variability between pages leads to an opportunity to easily trade off capacity and performance [4, 9].”