Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors

By David M. Brooks, Pradip Bose, S. Schuster, H. Jacobson, P. Kudva, Alper Buyuktosunoglu, J. Wellman, V. Zyuban, M. Gupta, P. Cook. IEEE Micro, 2000

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Techniques for Multicore Thermal Management: Classification and New Exploration (2006, methodology): “PowerTimer [4] is a parameterizable power estimation tool which operates in conjunction with Turandot.”
Speed scaling to manage energy and temperature (2007, methodology): “In other settings, the system may impose deadlines to better manage tasks or insure a certain quality of service to each task [Buttazzo 1997]. Yao et al. [1995] assumed that tasks can be preempted, that is, the device can suspend the execution of a task, and later resume the task from the point of s”
Optimizing pipelines for power and performance (2002, methodology): “Optimizing Pipelines for Power and Performance Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor Zyuban, Philip N. Strenski, Philip G. Emma IBM T.J. Watson Research Center Yorktown Heights, NY 10598 Abstract During the concept phase and definition of next gen- eration high-end p”
Cloud computing: state-of-the-art and research challenges (2010, background): “For example, energyefficient hardware architecture that enables slowing down CPU speeds and turning off partial hardware components [8] has become commonplace.”
The impact of technology scaling on lifetime reliability (2004, methodology): “To estimate dynamic power dissipation, we use the PowerTimer toolset [ 5 ] developed at IBM T.J.”