Private Circuits: Securing Hardware against Probing Attacks

By Yuval Ishai, Amit Sahai, David A. Wagner. Annual International Cryptology Conference, 2003

1,165 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/0ec3f92c0794cf054ec1cc2f0d4f243c1732308a

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Citations in the corpus

Masking against Side-Channel Attacks: A Formal Security Proof (2013, methodology): “In this paper, we prove the security of the scheme described in [3] with a secure multiplication processing close to those of [14,21], and with additional mask-refreshing computations.”
A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks (extended version) (2009, background): “fault attacks) and combined with other approaches for modeling physical attacks such as [16, 20, 21].”
Public-Key Cryptosystems Resilient to Key Leakage (2009, background): “[20,21] considered the more general problem of protecting privacy in circuits, where the adversary can access a bounded number of wires in the circuit.”
Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches (2011, background): “This can be done at the algorithm level [1,5,13,25], at the gate level [15,38] or even in combination with circuit design approaches [27].”
Physically Observable Cryptography (Extended Abstract) (2004, background): “Such restrictions may enable schemes that are more efficient or rely on weaker assumptions, while retaining security against meaningful physical observations attacks.”
Simultaneous Hardcore Bits and Cryptography against Memory Attacks (2009, background): “The works of [26, 25, 10] can be construed in this light.”
Threshold Implementations Against Side-Channel Attacks and Glitches (2006, background): “This can be done both at the algorithm level [2, 5, 10, 18] and at the gate level [12, 25].”
BiTR: Built-in Tamper Resilience (2011, background): “To address these attacks, starting with the work of [27, 33] there has been a surge of recent research activity on leakage-resilient cryptographic schemes.”
Strong Non-Interference and Type-Directed Higher-Order Masking (2016, background): “We have considered security in the probing model of Ishai, Sahai and Wagner [25], which is particularly well-suited to automated analysis due to its tight relation to probabilistic non-interference.”
Domain-Oriented Masking: Compact Masked Hardware Implementations with Arbitrary Protection Order (2016, methodology): “[15] but without the vulnerability to glitches, and it has a balanced arrangement of the multiplication terms which shortens the signal delay paths.”
Provably Secure Higher-Order Masking of AES (2010, methodology): “As mentioned above, only three methods exist in the literature that have been respectively proposed by Ishai, Sahai and Wagner [18], by Schramm and Paar [38] (secure only for d 6 2) and by Rivain, Dottax and Prouff [34] (dedicated to d = 2).”
Side-Channel Leakage of Masked CMOS Gates (2005, methodology): “The theory of masking at the gate level has been analyzed recently in [9].”
Leakage-Resilient Public-Key Cryptography in the Bounded-Retrieval Model (2009, neutral): “[17].”
Leakage-Resilient Cryptography (2008, background): “[19, 18] consider the more general case of making circuits provably secure [19] and even tamper resistant [18] against adversaries who can read/tamper the value”