HyGCN: A GCN Accelerator with Hybrid Architecture

By Mingyu Yan, Lei Deng, Xing Hu, Ling Liang, Yujing Feng, Xiaochun Ye, Zhimin Zhang, Dongrui Fan, Yuan Xie. International Symposium on High-Performance Computer Architecture, 2020

351 citations recorded by the source corpus.

Inspired by the great success of neural networks, graph convolutional neural networks (GCNs) are proposed to analyze graph data. GCNs mainly include two phases with distinct execution patterns. The Aggregation phase, behaves as graph processing, showing a dynamic and irregular execution pattern. The Combination phase, acts more like the neural networks, presenting a static and regular execution pattern. The hybrid execution patterns of GCNs require a design that alleviates irregularity and exploits regularity. Moreover, to achieve higher performance and energy efficiency, the design needs to leverage the high intra-vertex parallelism in Aggregation phase, the highly reusable inter-vertex data in Combination phase, and the opportunity to fuse phase-by-phase execution introduced by the new features of GCNs. However, existing architectures fail to address these demands. In this work, we first characterize the hybrid execution patterns of GCNs on Intel Xeon CPU. Guided by the characterization, we design a GCN accelerator, HyGCN, using a hybrid architecture to efficiently perform GCNs. Specifically, first, we build a new programming model to exploit the fine-grained parallelism for our hardware design. Second, we propose a hardware design with two efficient processing engines to alleviate the irregularity of Aggregation phase and leverage the regularity of Combination phase. Besides, these engines can exploit various parallelism and reuse highly reusable data efficiently. Third, we optimize the overall system via inter-engine pipeline for inter-phase fusion and priority-based off-chip memory access coordination to improve off-chip bandwidth utilization. Compared to the state-of-the-art software framework running on Intel Xeon CPU and NVIDIA V100 GPU, our work achieves on average 1509× speedup with 2500× energy reduction and average 6.5× speedup with 10× energy reduction, respectively.

Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/f3058ac35927720d2a229984b10524e36d87d7dc

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Artificial Intelligence

1. Song Han
2. Hanrui Wang
3. Kuan Wang
4. Shuai Che
5. Nizar Bouguila
6. Saeed Rahmani
7. Asiye Baghbani
8. Jiacheng Yang

In Computer Vision and Pattern Recognition

1. Song Han
2. Hanrui Wang
3. Kuan Wang
4. Shuai Che
5. Nizar Bouguila
6. Saeed Rahmani
7. Asiye Baghbani
8. Runbin Shi

In Hardware and Architecture

1. Shuai Che
2. Song Han
3. Steven K. Reinhardt
4. Hanrui Wang
5. Michael Nicolaidis

Citations in the corpus

• AWB-GCN: A Graph Convolutional Network Accelerator with Runtime Workload Rebalancing (2019, methodology): “We also compare AWB-GCN with prior work on GCNs such as HyGCN [31].”
• GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning (2020, background): “There are also accelerators [21], [22] focusing on GNN related workloads.”
• Graph Neural Networks for Intelligent Transportation Systems: A Survey (2023, methodology): “The graph awareness approach, which means being aware of the graph characteristics like its size and input features dimension, has proved to be useful for speeding up GNNs [213], [214].”