A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity

By Giacomo Indiveri, Elisabetta Chicca, Rodney J. Douglas. IEEE Transactions on Neural Networks, 2006

920 citations recorded by the source corpus.

Subfields: Cellular and Molecular Neuroscience, Cognitive Neuroscience, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/fcb912ee570d70f7d052dca7e753036f509cfca4

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In Cellular and Molecular Neuroscience

In Cognitive Neuroscience

In Electrical and Electronic Engineering

Citations in the corpus

Unsupervised learning of digit recognition using spike-timing-dependent plasticity (2015, methodology): “If our network were implemented on a low-power neuromorphic chip [3, 4, 5, 6], it could be run on a very low power budget; for example, using IBM’s TrueNorth chip [6] which consumes about 72mW for 1 million neurons, the network would consume less than 1mW.”
Neuromorphic Electronic Circuits for Building Autonomous Cognitive Systems (2014, methodology): “This is the condition for linearity, under which the circuit starts to behave as a first order low-pass filter, as described in Section II.”
Memory and Information Processing in Neuromorphic Systems (2015, background): “[115], [116], [117], [118], [119]; a large set of spike-based learning circuits have been proposed to model long-term plasticity [120], [121], [122], [123], [77], [124], [125], [126], [127], [128], [91]; multiple solutions have been proposed for implementing homeostatic plasticity mechanisms [129], ”
A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses (2015, methodology): “Themain novelty of the work proposed, compared to previous analogous approaches (Indiveri et al., 2006; Giulioni et al., 2008; Ramakrishnan et al., 2012; Yu et al., 2012) consists in the integration of analog bi-stable learning synapse circuits with asynchronous digital logic cells and in the…”
An Electronic Synapse Device Based on Metal Oxide Resistive Switching Memory for Neuromorphic Computation (2011, methodology): “Electronic synapse was first made by the circuits with tens of CMOS transistors and capacitors [10], which occupied signifi-”
Memristor-based neural networks (2013, methodology): “Voltage-controlled memristive nanodevices were utilized as synapses, the memristive conductance was used as the synaptic efﬁcacy and the CMOS-based platform used conventional integrate-and-ﬁre neurons [85].”
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons (2011, background): “A number of previous approaches implementing networks of spiking neurons in silicon [4][5][6] utilize analog circuit”
Finding a roadmap to achieve large neuromorphic hardware systems (2013, background): “Table 1 shows the structure presented in this paper results in the best synaptic density over other ICs built to date (Indiveri et al., 2006; Schemmel et al., 2006, 2008b; Camilleri et al., 2007; Brink et al., 2012).”