A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

By Jae-sun Seo, B. Brezzo, Yong Liu, B. Parker, Steven K. Esser, R. Montoye, Bipin Rajendran, J. Tierno, Leland Chang, Dharmendra S. Modha and 1 more. IEEE Custom Integrated Circuits Conference, 2011

313 citations recorded by the source corpus.

Subfields: Cellular and Molecular Neuroscience, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/a929bfd35293290cc0da49143c5711b81493f826

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In Cellular and Molecular Neuroscience

In Electrical and Electronic Engineering

Citations in the corpus

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory (2016, unknown): “There are also many other studies on accelerating NNs on the platforms of GPU [16], [41], [42], FPGA [43], [44], [45] and ASIC [17], [18], [19], [36], [37], [46].”
A 0.086-mm$^2$ 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS (2018, methodology): “ith core analog neuron and synapse computation and high-speed digital periphery are grouped on the left [23]– [25], [27], [63], [64], digital designs are grouped together with ODIN on the right [16], [28]–[31]. Toward efﬁcient spiking neuromorphic experimentation platforms, the key ﬁgures of merit a”
Neuromorphic Electronic Circuits for Building Autonomous Cognitive Systems (2014, background): “circuitry is needed for the stochastic state transitions [86].”
Deep Learning in Spiking Neural Networks (2018, background): “This same advantage is maintained in hardware (Carrillo et al., 2013, 2012;Merolla et al., 2014; Seo et al., 2011).”
A Survey of Neuromorphic Computing and Neural Networks in Hardware (2017, unknown): “implementations, is a full custom ASIC design [1562]–[1569].”
SPINDLE: SPINtronic Deep Learning Engine for large-scale neuromorphic computing (2014, background): “In addition, there have been eﬀorts to more faith-fully mimic biological neurons in CMOS circuits to achieve greater computational capability and eﬃciency [20,21].”
Neuromorphic computing using non-volatile memory (2017, methodology): “Without NVM, synaptic weight is typically stored in analog or digital devices such as capacitors [51–54], 4-bit SRAM [55], 8T SRAM [56], 1-bit SRAM [57], SRAM with 8b-11b per synapse [58] and oﬀ-die SDRAM [59].”
Loihi: A Neuromorphic Manycore Processor with On-Chip Learning (2018, methodology): “Some implementations have explored creative solutions to this problem, 12 but, in general, these approaches constrain network topologies and are not scalable.”
Broadcast and Weight: An Integrated Network For Scalable Photonic Spike Processing (2014, methodology): “Spiking primitives have been built in both CMOS analog circuits [10], digital " neurosynaptic cores " [11], and non-CMOS devices [12].”
Learning in spiking neural networks (2013, background): “The goal of this project is to design a neuromorphic chip which is able to replicate a mammalian brain in size, functionality and power consumption: it should be able to recreate 1010 neurons with 1014 synapses consuming 1KW of electrical power and occupying 2dm3 (liters) of space (Seo et al., 2011;”