Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors
By Chi-Keung Luk. Proceedings 28th Annual International Symposium on Computer Architecture, 2001
305 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/f8eaea91a1d5a730856fa39fa61f6f85400d5884
How researchers see this paper
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In Computer Networks and Communications
- Onur Mutlu
- Yale N. Patt
- Chris Wilkerson
- Jared Stark
- Yoongu Kim
- Jeremie S. Kim
- Vivek Seshadri
- Gabriel H. Loh
In Electrical and Electronic Engineering
In Hardware and Architecture
- Onur Mutlu
- Yale N. Patt
- Chris Wilkerson
- Jared Stark
- Yoongu Kim
- Jeremie S. Kim
- Vivek Seshadri
- Saugata Ghose
Citations in the corpus
- Runahead execution: an alternative to very large instruction windows for out-of-order processors (2003, methodology): “Thread-based prefetching techniques [8, 21, 31] use idle thread contexts on a multithreaded processor to run threads that help the primary thread [6].”