Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance

By Navab Singh, F. Y. Lim, W. Fang, S. C. Rustagi, L. Bera, A. Agarwal, C. Tung, K. Hoe, S. R. Omampuliyur, D. Tripathi and 4 more. International Electron Devices Meeting, 2006

163 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/e5f74b8b20370477fbc6c7699074130243932f88

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In Biomedical Engineering

1. Gerhard Klimeck
2. Neophytos Neophytou
3. Mark S. Lundstrom
4. K. Rumpf
5. P. Granitzer

In Electrical and Electronic Engineering

1. Gerhard Klimeck
2. Neophytos Neophytou
3. Edward J. Nowak
4. Mark S. Lundstrom
5. Anisur Rahman
6. Jing Guo
7. Mathieu Luisier
8. K. Rumpf

Citations in the corpus

• Bandstructure Effects in Silicon Nanowire Electron Transport (2007, background): “Nanowire transistors of diameters even down to 3nm have already been demonstrated by various experimental groups [2-4].”
• Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures (2019, background): “performance requirements if the proper channel dimension is chosen [38]–[40].”
• Carbon Nanotubes for High-Performance Electronics - Progress and Prospect (2008, unknown): “While gate-all-around silicon nanowire FETs with excellent performance specs have already been demonstrated [18], [19], experimental demonstration of a Fig.”