Cambricon: An Instruction Set Architecture for Neural Networks

By Shaoli Liu, Zidong Du, Jinhua Tao, Dong Han, Tao Luo, Yuan Xie, Yunji Chen, Tianshi Chen. 2016

315 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

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In Computer Vision and Pattern Recognition

In Electrical and Electronic Engineering

Citations in the corpus

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory (2016, unknown): “The DianNao series [17], [18], [46] are good examples of ASICbased NN accelerators; furthermore, the first instruction set architecture for NN accelerators has been proposed, called DianNaoYu [47].”
A Survey on Federated Learning for Resource-Constrained IoT Devices (2021, unknown): “The works in this area can be categorized in the domain of novel instructions for executing ML in the CPU [188], [189], design of specialized accelerators [190]–[192], optimized software library [193], [194], development of new memory technologies [195], and near data processing to enable large…”
RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing (2019, background): “Most research efforts within the architecture community have focused on accelerating the compute-intensive, highly-regular computational patterns found in fully-connected (FC), convolution (CNN), and recurrent (RNN) neural networks [5], [6], [10], [15], [18], [24], [27], [34], [39], [42], [48], [56]”
The Deep Learning Compiler: A Comprehensive Survey (2020, methodology): “erators also maintain their specific kernel libraries [22], [23].”
A Configurable Cloud-Scale DNN Processor for Real-Time AI (2018, background): “For example, Cambricon [49] is a load-store architecture that integrates data types such as scalars, vectors, matrices and control instructions to provide coverage for a wide range of DNNs to achieve higher code density than general-purpose ISAs as well as cover a wider range of models than…”
Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks (2020, background): “The need for higher speed and efficiency in DNN execution has led to an explosion of DNN accelerators [1, 3, 71–93] that has even made their way to operational datacenters (Google’s TPU [1], NVIDIA T4 [2], Microsoft Brainwave [3], etc.”
Towards Accurate Binary Convolutional Neural Network (2017, methodology): “Also, it would be interesting to investigate using FPGA/ASIC or other customized deep learning processor [Liu et al., 2016] to implement ABC-Net at run-time.”
DRISA: A DRAM-based Reconfigurable In-Situ Accelerator (2017, background): “9% of the operations can be aggregated as vector operations [61].”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, unknown): “[17], TrueNorth [18–20], MT-spike [21], PT-spike [22] DNN Co-processor NPU [23], DianNao-family [24–27], Cambricon [28], Cambricon-x [29], TPU [30,31], ScaleDeep [32], Stripes [33], Neural Cache [123,124], Diffy [125] FPGA FPGA-DCNN [34], Embedded-FPGA-CNN [35], FPGA-Exploration [36],…”
DeepStore: In-Storage Acceleration for Intelligent Queries (2019, methodology): “DNN Accelerator: Several accelerator designs have been proposed to speed up the training and inference computation of popular DNN models [28, 29, 34, 44, 49, 50, 52, 60, 65, 68, 71, 75, 78].”
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference (2019, background): “workloads in particular have received tremendous attention because of their pervasiveness in many application domains and high performance demands. Several architectures have been proposed,bothdigital[20,21,36,61,72,89]andmixeddigitalanalog using memristor crossbars [22, 23, 73, 95, 100]. arXiv:1901”
A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets (2018, background): “ized for performance and training. The streaming nature of the co-processor alleviates the need for a register ﬁle which is a common bottleneck in SIMD architectures and thus limits their scalability [33]. The architecture of NTX is depicted in Figure 3. It consists of four main blocks: (i) the FPU ”
From high-level deep neural models to FPGAs (2016, methodology): “[42] propose an ISA for neural networks optimized for high code density over vector and matrix operations.”
Edge Computing for Autonomous Driving: Opportunities and Challenges (2019, background): “[41] proposed a novel domain-specific instruction set architecture (ISA) for neural network accelerators.”